
kruska:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400540 <_init>:
  400540:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400544:	910003fd 	mov	x29, sp
  400548:	9400003c 	bl	400638 <call_weak_fn>
  40054c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400550:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400560 <.plt>:
  400560:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400564:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x10230>
  400568:	f947fe11 	ldr	x17, [x16, #4088]
  40056c:	913fe210 	add	x16, x16, #0xff8
  400570:	d61f0220 	br	x17
  400574:	d503201f 	nop
  400578:	d503201f 	nop
  40057c:	d503201f 	nop

0000000000400580 <__libc_start_main@plt>:
  400580:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400584:	f9400211 	ldr	x17, [x16]
  400588:	91000210 	add	x16, x16, #0x0
  40058c:	d61f0220 	br	x17

0000000000400590 <__gmon_start__@plt>:
  400590:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400594:	f9400611 	ldr	x17, [x16, #8]
  400598:	91002210 	add	x16, x16, #0x8
  40059c:	d61f0220 	br	x17

00000000004005a0 <abort@plt>:
  4005a0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4005a4:	f9400a11 	ldr	x17, [x16, #16]
  4005a8:	91004210 	add	x16, x16, #0x10
  4005ac:	d61f0220 	br	x17

00000000004005b0 <puts@plt>:
  4005b0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4005b4:	f9400e11 	ldr	x17, [x16, #24]
  4005b8:	91006210 	add	x16, x16, #0x18
  4005bc:	d61f0220 	br	x17

00000000004005c0 <__isoc99_scanf@plt>:
  4005c0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4005c4:	f9401211 	ldr	x17, [x16, #32]
  4005c8:	91008210 	add	x16, x16, #0x20
  4005cc:	d61f0220 	br	x17

00000000004005d0 <printf@plt>:
  4005d0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4005d4:	f9401611 	ldr	x17, [x16, #40]
  4005d8:	9100a210 	add	x16, x16, #0x28
  4005dc:	d61f0220 	br	x17

00000000004005e0 <putchar@plt>:
  4005e0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4005e4:	f9401a11 	ldr	x17, [x16, #48]
  4005e8:	9100c210 	add	x16, x16, #0x30
  4005ec:	d61f0220 	br	x17

Disassembly of section .text:

00000000004005f0 <_start>:
  4005f0:	d280001d 	mov	x29, #0x0                   	// #0
  4005f4:	d280001e 	mov	x30, #0x0                   	// #0
  4005f8:	aa0003e5 	mov	x5, x0
  4005fc:	f94003e1 	ldr	x1, [sp]
  400600:	910023e2 	add	x2, sp, #0x8
  400604:	910003e6 	mov	x6, sp
  400608:	580000c0 	ldr	x0, 400620 <_start+0x30>
  40060c:	580000e3 	ldr	x3, 400628 <_start+0x38>
  400610:	58000104 	ldr	x4, 400630 <_start+0x40>
  400614:	97ffffdb 	bl	400580 <__libc_start_main@plt>
  400618:	97ffffe2 	bl	4005a0 <abort@plt>
  40061c:	00000000 	.inst	0x00000000 ; undefined
  400620:	00400b38 	.word	0x00400b38
  400624:	00000000 	.word	0x00000000
  400628:	00400cb0 	.word	0x00400cb0
  40062c:	00000000 	.word	0x00000000
  400630:	00400d30 	.word	0x00400d30
  400634:	00000000 	.word	0x00000000

0000000000400638 <call_weak_fn>:
  400638:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x10230>
  40063c:	f947f000 	ldr	x0, [x0, #4064]
  400640:	b4000040 	cbz	x0, 400648 <call_weak_fn+0x10>
  400644:	17ffffd3 	b	400590 <__gmon_start__@plt>
  400648:	d65f03c0 	ret
  40064c:	00000000 	.inst	0x00000000 ; undefined

0000000000400650 <deregister_tm_clones>:
  400650:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400654:	91012000 	add	x0, x0, #0x48
  400658:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  40065c:	91012021 	add	x1, x1, #0x48
  400660:	eb00003f 	cmp	x1, x0
  400664:	540000a0 	b.eq	400678 <deregister_tm_clones+0x28>  // b.none
  400668:	90000001 	adrp	x1, 400000 <_init-0x540>
  40066c:	f946a821 	ldr	x1, [x1, #3408]
  400670:	b4000041 	cbz	x1, 400678 <deregister_tm_clones+0x28>
  400674:	d61f0020 	br	x1
  400678:	d65f03c0 	ret
  40067c:	d503201f 	nop

0000000000400680 <register_tm_clones>:
  400680:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400684:	91012000 	add	x0, x0, #0x48
  400688:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  40068c:	91012021 	add	x1, x1, #0x48
  400690:	cb000021 	sub	x1, x1, x0
  400694:	9343fc21 	asr	x1, x1, #3
  400698:	8b41fc21 	add	x1, x1, x1, lsr #63
  40069c:	9341fc21 	asr	x1, x1, #1
  4006a0:	b40000a1 	cbz	x1, 4006b4 <register_tm_clones+0x34>
  4006a4:	90000002 	adrp	x2, 400000 <_init-0x540>
  4006a8:	f946ac42 	ldr	x2, [x2, #3416]
  4006ac:	b4000042 	cbz	x2, 4006b4 <register_tm_clones+0x34>
  4006b0:	d61f0040 	br	x2
  4006b4:	d65f03c0 	ret

00000000004006b8 <__do_global_dtors_aux>:
  4006b8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006bc:	910003fd 	mov	x29, sp
  4006c0:	f9000bf3 	str	x19, [sp, #16]
  4006c4:	d0000093 	adrp	x19, 412000 <__libc_start_main@GLIBC_2.17>
  4006c8:	39412260 	ldrb	w0, [x19, #72]
  4006cc:	35000080 	cbnz	w0, 4006dc <__do_global_dtors_aux+0x24>
  4006d0:	97ffffe0 	bl	400650 <deregister_tm_clones>
  4006d4:	52800020 	mov	w0, #0x1                   	// #1
  4006d8:	39012260 	strb	w0, [x19, #72]
  4006dc:	f9400bf3 	ldr	x19, [sp, #16]
  4006e0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4006e4:	d65f03c0 	ret

00000000004006e8 <frame_dummy>:
  4006e8:	17ffffe6 	b	400680 <register_tm_clones>

00000000004006ec <kruska>:
  4006ec:	d100c3ff 	sub	sp, sp, #0x30
  4006f0:	f90007e0 	str	x0, [sp, #8]
  4006f4:	52800020 	mov	w0, #0x1                   	// #1
  4006f8:	b90027e0 	str	w0, [sp, #36]
  4006fc:	52800020 	mov	w0, #0x1                   	// #1
  400700:	b90023e0 	str	w0, [sp, #32]
  400704:	52800020 	mov	w0, #0x1                   	// #1
  400708:	b9002fe0 	str	w0, [sp, #44]
  40070c:	14000029 	b	4007b0 <kruska+0xc4>
  400710:	52800020 	mov	w0, #0x1                   	// #1
  400714:	b9002be0 	str	w0, [sp, #40]
  400718:	14000020 	b	400798 <kruska+0xac>
  40071c:	b9402fe1 	ldr	w1, [sp, #44]
  400720:	b9402be0 	ldr	w0, [sp, #40]
  400724:	6b00003f 	cmp	w1, w0
  400728:	540001c1 	b.ne	400760 <kruska+0x74>  // b.any
  40072c:	f94007e2 	ldr	x2, [sp, #8]
  400730:	b9802be3 	ldrsw	x3, [sp, #40]
  400734:	b9802fe1 	ldrsw	x1, [sp, #44]
  400738:	aa0103e0 	mov	x0, x1
  40073c:	d37df000 	lsl	x0, x0, #3
  400740:	cb010000 	sub	x0, x0, x1
  400744:	8b030000 	add	x0, x0, x3
  400748:	9100c000 	add	x0, x0, #0x30
  40074c:	d37ef400 	lsl	x0, x0, #2
  400750:	8b000040 	add	x0, x2, x0
  400754:	52800021 	mov	w1, #0x1                   	// #1
  400758:	b9000c01 	str	w1, [x0, #12]
  40075c:	1400000c 	b	40078c <kruska+0xa0>
  400760:	f94007e2 	ldr	x2, [sp, #8]
  400764:	b9802be3 	ldrsw	x3, [sp, #40]
  400768:	b9802fe1 	ldrsw	x1, [sp, #44]
  40076c:	aa0103e0 	mov	x0, x1
  400770:	d37df000 	lsl	x0, x0, #3
  400774:	cb010000 	sub	x0, x0, x1
  400778:	8b030000 	add	x0, x0, x3
  40077c:	9100c000 	add	x0, x0, #0x30
  400780:	d37ef400 	lsl	x0, x0, #2
  400784:	8b000040 	add	x0, x2, x0
  400788:	b9000c1f 	str	wzr, [x0, #12]
  40078c:	b9402be0 	ldr	w0, [sp, #40]
  400790:	11000400 	add	w0, w0, #0x1
  400794:	b9002be0 	str	w0, [sp, #40]
  400798:	b9402be0 	ldr	w0, [sp, #40]
  40079c:	7100181f 	cmp	w0, #0x6
  4007a0:	54fffbed 	b.le	40071c <kruska+0x30>
  4007a4:	b9402fe0 	ldr	w0, [sp, #44]
  4007a8:	11000400 	add	w0, w0, #0x1
  4007ac:	b9002fe0 	str	w0, [sp, #44]
  4007b0:	b9402fe0 	ldr	w0, [sp, #44]
  4007b4:	7100181f 	cmp	w0, #0x6
  4007b8:	54fffacd 	b.le	400710 <kruska+0x24>
  4007bc:	140000a2 	b	400a44 <kruska+0x358>
  4007c0:	52800020 	mov	w0, #0x1                   	// #1
  4007c4:	b9002fe0 	str	w0, [sp, #44]
  4007c8:	14000041 	b	4008cc <kruska+0x1e0>
  4007cc:	52800020 	mov	w0, #0x1                   	// #1
  4007d0:	b9002be0 	str	w0, [sp, #40]
  4007d4:	14000038 	b	4008b4 <kruska+0x1c8>
  4007d8:	f94007e2 	ldr	x2, [sp, #8]
  4007dc:	b98023e1 	ldrsw	x1, [sp, #32]
  4007e0:	aa0103e0 	mov	x0, x1
  4007e4:	d37ff800 	lsl	x0, x0, #1
  4007e8:	8b010000 	add	x0, x0, x1
  4007ec:	d37ef400 	lsl	x0, x0, #2
  4007f0:	8b000040 	add	x0, x2, x0
  4007f4:	b9404800 	ldr	w0, [x0, #72]
  4007f8:	b9402be1 	ldr	w1, [sp, #40]
  4007fc:	6b00003f 	cmp	w1, w0
  400800:	54000201 	b.ne	400840 <kruska+0x154>  // b.any
  400804:	f94007e2 	ldr	x2, [sp, #8]
  400808:	b9802be3 	ldrsw	x3, [sp, #40]
  40080c:	b9802fe1 	ldrsw	x1, [sp, #44]
  400810:	aa0103e0 	mov	x0, x1
  400814:	d37df000 	lsl	x0, x0, #3
  400818:	cb010000 	sub	x0, x0, x1
  40081c:	8b030000 	add	x0, x0, x3
  400820:	9100c000 	add	x0, x0, #0x30
  400824:	d37ef400 	lsl	x0, x0, #2
  400828:	8b000040 	add	x0, x2, x0
  40082c:	b9400c00 	ldr	w0, [x0, #12]
  400830:	7100041f 	cmp	w0, #0x1
  400834:	54000061 	b.ne	400840 <kruska+0x154>  // b.any
  400838:	b9402fe0 	ldr	w0, [sp, #44]
  40083c:	b9001fe0 	str	w0, [sp, #28]
  400840:	f94007e2 	ldr	x2, [sp, #8]
  400844:	b98023e1 	ldrsw	x1, [sp, #32]
  400848:	aa0103e0 	mov	x0, x1
  40084c:	d37ff800 	lsl	x0, x0, #1
  400850:	8b010000 	add	x0, x0, x1
  400854:	d37ef400 	lsl	x0, x0, #2
  400858:	8b000040 	add	x0, x2, x0
  40085c:	b9404c00 	ldr	w0, [x0, #76]
  400860:	b9402be1 	ldr	w1, [sp, #40]
  400864:	6b00003f 	cmp	w1, w0
  400868:	54000201 	b.ne	4008a8 <kruska+0x1bc>  // b.any
  40086c:	f94007e2 	ldr	x2, [sp, #8]
  400870:	b9802be3 	ldrsw	x3, [sp, #40]
  400874:	b9802fe1 	ldrsw	x1, [sp, #44]
  400878:	aa0103e0 	mov	x0, x1
  40087c:	d37df000 	lsl	x0, x0, #3
  400880:	cb010000 	sub	x0, x0, x1
  400884:	8b030000 	add	x0, x0, x3
  400888:	9100c000 	add	x0, x0, #0x30
  40088c:	d37ef400 	lsl	x0, x0, #2
  400890:	8b000040 	add	x0, x2, x0
  400894:	b9400c00 	ldr	w0, [x0, #12]
  400898:	7100041f 	cmp	w0, #0x1
  40089c:	54000061 	b.ne	4008a8 <kruska+0x1bc>  // b.any
  4008a0:	b9402fe0 	ldr	w0, [sp, #44]
  4008a4:	b9001be0 	str	w0, [sp, #24]
  4008a8:	b9402be0 	ldr	w0, [sp, #40]
  4008ac:	11000400 	add	w0, w0, #0x1
  4008b0:	b9002be0 	str	w0, [sp, #40]
  4008b4:	b9402be0 	ldr	w0, [sp, #40]
  4008b8:	7100181f 	cmp	w0, #0x6
  4008bc:	54fff8ed 	b.le	4007d8 <kruska+0xec>
  4008c0:	b9402fe0 	ldr	w0, [sp, #44]
  4008c4:	11000400 	add	w0, w0, #0x1
  4008c8:	b9002fe0 	str	w0, [sp, #44]
  4008cc:	b9402fe0 	ldr	w0, [sp, #44]
  4008d0:	7100181f 	cmp	w0, #0x6
  4008d4:	54fff7cd 	b.le	4007cc <kruska+0xe0>
  4008d8:	b9401fe1 	ldr	w1, [sp, #28]
  4008dc:	b9401be0 	ldr	w0, [sp, #24]
  4008e0:	6b00003f 	cmp	w1, w0
  4008e4:	54000aa0 	b.eq	400a38 <kruska+0x34c>  // b.none
  4008e8:	f94007e2 	ldr	x2, [sp, #8]
  4008ec:	b98027e1 	ldrsw	x1, [sp, #36]
  4008f0:	aa0103e0 	mov	x0, x1
  4008f4:	d37ff800 	lsl	x0, x0, #1
  4008f8:	8b010000 	add	x0, x0, x1
  4008fc:	d37ef400 	lsl	x0, x0, #2
  400900:	8b000043 	add	x3, x2, x0
  400904:	f94007e2 	ldr	x2, [sp, #8]
  400908:	b98023e1 	ldrsw	x1, [sp, #32]
  40090c:	aa0103e0 	mov	x0, x1
  400910:	d37ff800 	lsl	x0, x0, #1
  400914:	8b010000 	add	x0, x0, x1
  400918:	d37ef400 	lsl	x0, x0, #2
  40091c:	8b000040 	add	x0, x2, x0
  400920:	91010000 	add	x0, x0, #0x40
  400924:	91002001 	add	x1, x0, #0x8
  400928:	aa0303e0 	mov	x0, x3
  40092c:	f9400022 	ldr	x2, [x1]
  400930:	f9000002 	str	x2, [x0]
  400934:	b9400821 	ldr	w1, [x1, #8]
  400938:	b9000801 	str	w1, [x0, #8]
  40093c:	b94027e0 	ldr	w0, [sp, #36]
  400940:	11000400 	add	w0, w0, #0x1
  400944:	b90027e0 	str	w0, [sp, #36]
  400948:	52800020 	mov	w0, #0x1                   	// #1
  40094c:	b9002be0 	str	w0, [sp, #40]
  400950:	14000037 	b	400a2c <kruska+0x340>
  400954:	f94007e2 	ldr	x2, [sp, #8]
  400958:	b9802be3 	ldrsw	x3, [sp, #40]
  40095c:	b9801fe1 	ldrsw	x1, [sp, #28]
  400960:	aa0103e0 	mov	x0, x1
  400964:	d37df000 	lsl	x0, x0, #3
  400968:	cb010000 	sub	x0, x0, x1
  40096c:	8b030000 	add	x0, x0, x3
  400970:	9100c000 	add	x0, x0, #0x30
  400974:	d37ef400 	lsl	x0, x0, #2
  400978:	8b000040 	add	x0, x2, x0
  40097c:	b9400c00 	ldr	w0, [x0, #12]
  400980:	7100001f 	cmp	w0, #0x0
  400984:	540001c1 	b.ne	4009bc <kruska+0x2d0>  // b.any
  400988:	f94007e2 	ldr	x2, [sp, #8]
  40098c:	b9802be3 	ldrsw	x3, [sp, #40]
  400990:	b9801be1 	ldrsw	x1, [sp, #24]
  400994:	aa0103e0 	mov	x0, x1
  400998:	d37df000 	lsl	x0, x0, #3
  40099c:	cb010000 	sub	x0, x0, x1
  4009a0:	8b030000 	add	x0, x0, x3
  4009a4:	9100c000 	add	x0, x0, #0x30
  4009a8:	d37ef400 	lsl	x0, x0, #2
  4009ac:	8b000040 	add	x0, x2, x0
  4009b0:	b9400c00 	ldr	w0, [x0, #12]
  4009b4:	7100001f 	cmp	w0, #0x0
  4009b8:	54000060 	b.eq	4009c4 <kruska+0x2d8>  // b.none
  4009bc:	52800021 	mov	w1, #0x1                   	// #1
  4009c0:	14000002 	b	4009c8 <kruska+0x2dc>
  4009c4:	52800001 	mov	w1, #0x0                   	// #0
  4009c8:	f94007e3 	ldr	x3, [sp, #8]
  4009cc:	b9802be4 	ldrsw	x4, [sp, #40]
  4009d0:	b9801fe2 	ldrsw	x2, [sp, #28]
  4009d4:	aa0203e0 	mov	x0, x2
  4009d8:	d37df000 	lsl	x0, x0, #3
  4009dc:	cb020000 	sub	x0, x0, x2
  4009e0:	8b040000 	add	x0, x0, x4
  4009e4:	9100c000 	add	x0, x0, #0x30
  4009e8:	d37ef400 	lsl	x0, x0, #2
  4009ec:	8b000060 	add	x0, x3, x0
  4009f0:	b9000c01 	str	w1, [x0, #12]
  4009f4:	f94007e2 	ldr	x2, [sp, #8]
  4009f8:	b9802be3 	ldrsw	x3, [sp, #40]
  4009fc:	b9801be1 	ldrsw	x1, [sp, #24]
  400a00:	aa0103e0 	mov	x0, x1
  400a04:	d37df000 	lsl	x0, x0, #3
  400a08:	cb010000 	sub	x0, x0, x1
  400a0c:	8b030000 	add	x0, x0, x3
  400a10:	9100c000 	add	x0, x0, #0x30
  400a14:	d37ef400 	lsl	x0, x0, #2
  400a18:	8b000040 	add	x0, x2, x0
  400a1c:	b9000c1f 	str	wzr, [x0, #12]
  400a20:	b9402be0 	ldr	w0, [sp, #40]
  400a24:	11000400 	add	w0, w0, #0x1
  400a28:	b9002be0 	str	w0, [sp, #40]
  400a2c:	b9402be0 	ldr	w0, [sp, #40]
  400a30:	7100181f 	cmp	w0, #0x6
  400a34:	54fff90d 	b.le	400954 <kruska+0x268>
  400a38:	b94023e0 	ldr	w0, [sp, #32]
  400a3c:	11000400 	add	w0, w0, #0x1
  400a40:	b90023e0 	str	w0, [sp, #32]
  400a44:	b94027e0 	ldr	w0, [sp, #36]
  400a48:	7100141f 	cmp	w0, #0x5
  400a4c:	54ffebad 	b.le	4007c0 <kruska+0xd4>
  400a50:	d503201f 	nop
  400a54:	9100c3ff 	add	sp, sp, #0x30
  400a58:	d65f03c0 	ret

0000000000400a5c <display>:
  400a5c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400a60:	910003fd 	mov	x29, sp
  400a64:	f9000fa0 	str	x0, [x29, #24]
  400a68:	b90017a1 	str	w1, [x29, #20]
  400a6c:	b90027bf 	str	wzr, [x29, #36]
  400a70:	52800020 	mov	w0, #0x1                   	// #1
  400a74:	b9002fa0 	str	w0, [x29, #44]
  400a78:	14000028 	b	400b18 <display+0xbc>
  400a7c:	52800020 	mov	w0, #0x1                   	// #1
  400a80:	b9002ba0 	str	w0, [x29, #40]
  400a84:	1400001f 	b	400b00 <display+0xa4>
  400a88:	f9400fa2 	ldr	x2, [x29, #24]
  400a8c:	b9802ba3 	ldrsw	x3, [x29, #40]
  400a90:	b9802fa1 	ldrsw	x1, [x29, #44]
  400a94:	aa0103e0 	mov	x0, x1
  400a98:	d37df000 	lsl	x0, x0, #3
  400a9c:	cb010000 	sub	x0, x0, x1
  400aa0:	8b030000 	add	x0, x0, x3
  400aa4:	9100c000 	add	x0, x0, #0x30
  400aa8:	d37ef400 	lsl	x0, x0, #2
  400aac:	8b000040 	add	x0, x2, x0
  400ab0:	b9400c01 	ldr	w1, [x0, #12]
  400ab4:	90000000 	adrp	x0, 400000 <_init-0x540>
  400ab8:	91358000 	add	x0, x0, #0xd60
  400abc:	97fffec5 	bl	4005d0 <printf@plt>
  400ac0:	b94027a0 	ldr	w0, [x29, #36]
  400ac4:	11000400 	add	w0, w0, #0x1
  400ac8:	b90027a0 	str	w0, [x29, #36]
  400acc:	b94027a0 	ldr	w0, [x29, #36]
  400ad0:	b94017a1 	ldr	w1, [x29, #20]
  400ad4:	1ac10c02 	sdiv	w2, w0, w1
  400ad8:	b94017a1 	ldr	w1, [x29, #20]
  400adc:	1b017c41 	mul	w1, w2, w1
  400ae0:	4b010000 	sub	w0, w0, w1
  400ae4:	7100001f 	cmp	w0, #0x0
  400ae8:	54000061 	b.ne	400af4 <display+0x98>  // b.any
  400aec:	52800140 	mov	w0, #0xa                   	// #10
  400af0:	97fffebc 	bl	4005e0 <putchar@plt>
  400af4:	b9402ba0 	ldr	w0, [x29, #40]
  400af8:	11000400 	add	w0, w0, #0x1
  400afc:	b9002ba0 	str	w0, [x29, #40]
  400b00:	b9402ba0 	ldr	w0, [x29, #40]
  400b04:	7100181f 	cmp	w0, #0x6
  400b08:	54fffc0d 	b.le	400a88 <display+0x2c>
  400b0c:	b9402fa0 	ldr	w0, [x29, #44]
  400b10:	11000400 	add	w0, w0, #0x1
  400b14:	b9002fa0 	str	w0, [x29, #44]
  400b18:	b9402fa0 	ldr	w0, [x29, #44]
  400b1c:	7100181f 	cmp	w0, #0x6
  400b20:	54fffaed 	b.le	400a7c <display+0x20>
  400b24:	52800140 	mov	w0, #0xa                   	// #10
  400b28:	97fffeae 	bl	4005e0 <putchar@plt>
  400b2c:	d503201f 	nop
  400b30:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400b34:	d65f03c0 	ret

0000000000400b38 <main>:
  400b38:	a9a57bfd 	stp	x29, x30, [sp, #-432]!
  400b3c:	910003fd 	mov	x29, sp
  400b40:	52800020 	mov	w0, #0x1                   	// #1
  400b44:	b901afa0 	str	w0, [x29, #428]
  400b48:	14000028 	b	400be8 <main+0xb0>
  400b4c:	90000000 	adrp	x0, 400000 <_init-0x540>
  400b50:	9135a000 	add	x0, x0, #0xd68
  400b54:	97fffe97 	bl	4005b0 <puts@plt>
  400b58:	910063a2 	add	x2, x29, #0x18
  400b5c:	b981afa1 	ldrsw	x1, [x29, #428]
  400b60:	aa0103e0 	mov	x0, x1
  400b64:	d37ff800 	lsl	x0, x0, #1
  400b68:	8b010000 	add	x0, x0, x1
  400b6c:	d37ef400 	lsl	x0, x0, #2
  400b70:	91010000 	add	x0, x0, #0x40
  400b74:	8b000040 	add	x0, x2, x0
  400b78:	91002004 	add	x4, x0, #0x8
  400b7c:	910063a2 	add	x2, x29, #0x18
  400b80:	b981afa1 	ldrsw	x1, [x29, #428]
  400b84:	aa0103e0 	mov	x0, x1
  400b88:	d37ff800 	lsl	x0, x0, #1
  400b8c:	8b010000 	add	x0, x0, x1
  400b90:	d37ef400 	lsl	x0, x0, #2
  400b94:	91010000 	add	x0, x0, #0x40
  400b98:	8b000040 	add	x0, x2, x0
  400b9c:	91003005 	add	x5, x0, #0xc
  400ba0:	910063a2 	add	x2, x29, #0x18
  400ba4:	b981afa1 	ldrsw	x1, [x29, #428]
  400ba8:	aa0103e0 	mov	x0, x1
  400bac:	d37ff800 	lsl	x0, x0, #1
  400bb0:	8b010000 	add	x0, x0, x1
  400bb4:	d37ef400 	lsl	x0, x0, #2
  400bb8:	91010000 	add	x0, x0, #0x40
  400bbc:	8b000040 	add	x0, x2, x0
  400bc0:	91004001 	add	x1, x0, #0x10
  400bc4:	90000000 	adrp	x0, 400000 <_init-0x540>
  400bc8:	91364000 	add	x0, x0, #0xd90
  400bcc:	aa0103e3 	mov	x3, x1
  400bd0:	aa0503e2 	mov	x2, x5
  400bd4:	aa0403e1 	mov	x1, x4
  400bd8:	97fffe7a 	bl	4005c0 <__isoc99_scanf@plt>
  400bdc:	b941afa0 	ldr	w0, [x29, #428]
  400be0:	11000400 	add	w0, w0, #0x1
  400be4:	b901afa0 	str	w0, [x29, #428]
  400be8:	b941afa0 	ldr	w0, [x29, #428]
  400bec:	7100281f 	cmp	w0, #0xa
  400bf0:	54fffaed 	b.le	400b4c <main+0x14>
  400bf4:	910063a0 	add	x0, x29, #0x18
  400bf8:	97fffebd 	bl	4006ec <kruska>
  400bfc:	52800020 	mov	w0, #0x1                   	// #1
  400c00:	b901afa0 	str	w0, [x29, #428]
  400c04:	14000024 	b	400c94 <main+0x15c>
  400c08:	b981afa1 	ldrsw	x1, [x29, #428]
  400c0c:	aa0103e0 	mov	x0, x1
  400c10:	d37ff800 	lsl	x0, x0, #1
  400c14:	8b010000 	add	x0, x0, x1
  400c18:	d37ef400 	lsl	x0, x0, #2
  400c1c:	910063a1 	add	x1, x29, #0x18
  400c20:	b8606821 	ldr	w1, [x1, x0]
  400c24:	90000000 	adrp	x0, 400000 <_init-0x540>
  400c28:	91368000 	add	x0, x0, #0xda0
  400c2c:	97fffe69 	bl	4005d0 <printf@plt>
  400c30:	b981afa1 	ldrsw	x1, [x29, #428]
  400c34:	aa0103e0 	mov	x0, x1
  400c38:	d37ff800 	lsl	x0, x0, #1
  400c3c:	8b010000 	add	x0, x0, x1
  400c40:	d37ef400 	lsl	x0, x0, #2
  400c44:	910073a1 	add	x1, x29, #0x1c
  400c48:	b8606821 	ldr	w1, [x1, x0]
  400c4c:	90000000 	adrp	x0, 400000 <_init-0x540>
  400c50:	9136c000 	add	x0, x0, #0xdb0
  400c54:	97fffe5f 	bl	4005d0 <printf@plt>
  400c58:	b981afa1 	ldrsw	x1, [x29, #428]
  400c5c:	aa0103e0 	mov	x0, x1
  400c60:	d37ff800 	lsl	x0, x0, #1
  400c64:	8b010000 	add	x0, x0, x1
  400c68:	d37ef400 	lsl	x0, x0, #2
  400c6c:	910083a1 	add	x1, x29, #0x20
  400c70:	b8606821 	ldr	w1, [x1, x0]
  400c74:	90000000 	adrp	x0, 400000 <_init-0x540>
  400c78:	91370000 	add	x0, x0, #0xdc0
  400c7c:	97fffe55 	bl	4005d0 <printf@plt>
  400c80:	52800140 	mov	w0, #0xa                   	// #10
  400c84:	97fffe57 	bl	4005e0 <putchar@plt>
  400c88:	b941afa0 	ldr	w0, [x29, #428]
  400c8c:	11000400 	add	w0, w0, #0x1
  400c90:	b901afa0 	str	w0, [x29, #428]
  400c94:	b941afa0 	ldr	w0, [x29, #428]
  400c98:	7100141f 	cmp	w0, #0x5
  400c9c:	54fffb6d 	b.le	400c08 <main+0xd0>
  400ca0:	d503201f 	nop
  400ca4:	a8db7bfd 	ldp	x29, x30, [sp], #432
  400ca8:	d65f03c0 	ret
  400cac:	00000000 	.inst	0x00000000 ; undefined

0000000000400cb0 <__libc_csu_init>:
  400cb0:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400cb4:	910003fd 	mov	x29, sp
  400cb8:	a901d7f4 	stp	x20, x21, [sp, #24]
  400cbc:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x10230>
  400cc0:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x10230>
  400cc4:	91374294 	add	x20, x20, #0xdd0
  400cc8:	913722b5 	add	x21, x21, #0xdc8
  400ccc:	a902dff6 	stp	x22, x23, [sp, #40]
  400cd0:	cb150294 	sub	x20, x20, x21
  400cd4:	f9001ff8 	str	x24, [sp, #56]
  400cd8:	2a0003f6 	mov	w22, w0
  400cdc:	aa0103f7 	mov	x23, x1
  400ce0:	9343fe94 	asr	x20, x20, #3
  400ce4:	aa0203f8 	mov	x24, x2
  400ce8:	97fffe16 	bl	400540 <_init>
  400cec:	b4000194 	cbz	x20, 400d1c <__libc_csu_init+0x6c>
  400cf0:	f9000bb3 	str	x19, [x29, #16]
  400cf4:	d2800013 	mov	x19, #0x0                   	// #0
  400cf8:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400cfc:	aa1803e2 	mov	x2, x24
  400d00:	aa1703e1 	mov	x1, x23
  400d04:	2a1603e0 	mov	w0, w22
  400d08:	91000673 	add	x19, x19, #0x1
  400d0c:	d63f0060 	blr	x3
  400d10:	eb13029f 	cmp	x20, x19
  400d14:	54ffff21 	b.ne	400cf8 <__libc_csu_init+0x48>  // b.any
  400d18:	f9400bb3 	ldr	x19, [x29, #16]
  400d1c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400d20:	a942dff6 	ldp	x22, x23, [sp, #40]
  400d24:	f9401ff8 	ldr	x24, [sp, #56]
  400d28:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400d2c:	d65f03c0 	ret

0000000000400d30 <__libc_csu_fini>:
  400d30:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400d34 <_fini>:
  400d34:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400d38:	910003fd 	mov	x29, sp
  400d3c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400d40:	d65f03c0 	ret
